The present invention relates to a nonvolatile semiconductor memory device (EEPROM) which is electrically erasable programmable, and more particularly to an EEPROM having at least one of auto-program and auto-erase functions, which is used as a batch-erase type semiconductor memory such as a NOR-type flash EEPROM.
The EEPROM is advantageous in that data in nonvolatile memory cells is not lost even if power is turned off, and a demand for EEPROMs has recently increased remarkably. In particular, a batch-erasable flash memory in which each memory cell is formed of one transistor is expected to be substituted for a large-capacity magnetic disk.
Memory cells used in a cell array of a conventional EEPROM are formed of NMOS-type field-effect transistors (cell transistors) each having a two-layer gate structure in which a floating gate, which is formed in a gate insulating film as a charge storage layer, and a control gate are stacked.
In this type of cell transistor, program characteristics or erase characteristics are deteriorated due to repeated program/erase operation at the time of use. Consequently, compared to the earliest time of use of the device, a program/erasing time increases and the amount of injection/release of electric charge in/from the floating gate decreases. As a result, the range of variation between the threshold voltage in the programmed state of the memory cell and the threshold voltage in the erased state thereof decreases.
In addition, with repetition of program/erase operations at the time of use, an electric field concentrates at the carriers trapped in the insulating film and insulation breakdown of the memory cell will take place. In such a case, it would be impossible to program/erase data in another cell which shares the control gate or source/drain region with the broken cell, or data would be erroneously read out from the memory cell.
For example, if a high program voltage is applied to the control gate shared by the broken cell, a leak current flows from the control gate to the semiconductor substrate through the insulating film of the broken cell. Consequently, problems such that the potential of the program voltage becomes lower than a predetermined level, the program operation is disabled or the power consumption increases, or the like, are occurred.
In the EEPROM, a program voltage and an erase voltage are produced by a high voltage generating circuit which boosts a power supply voltage Vcc to obtain a high voltage. The high voltage generating circuit is constituted by a booster circuit, which comprises a charge pump circuits cascade-connected in multi-stages, and a voltage limiting circuit connected to the final-stage charge pump circuit in the booster circuit.
In the above-described EEPROM, when data is to be programmed, the greater the number of times of applications of program pulses having a constant voltage and a constant pulse width, the greater the amount of charge programmed into the floating gate electrode. In this case, in an intelligent program method adopted to prevent overprogram, data program is effected little by little in a plurality of operations by controlling the number of times of applications of program pulses. A data program operation and a data read operation following the data program operation are repeated, and the program operation is completed when the read data has become equal to the programmed data.
On the other hand, in the field of semiconductor memories including latest large-capacity EEPROMs, provision of a redundancy circuit is essential in order to increase the manufacturing yield. According to the redundancy technique, in addition to an ordinary memory cell array (regular memory cell array), a redundancy memory cell array for relieving, e.g. a defect of the regular memory cell array, and a redundancy address decoder (programmable decoder) for selecting rows of the redundancy memory cell array are provided on the same semiconductor chip. Thus, a defective memory cell of the regular memory cell array, which is found in a test step of the manufacture, is relieved.
As regards latest flash EEPROMs, there is an increasing demand for products adopting a single power supply system wherein no special external power supply is provided for data program/erase. In such flash EEPROMs, when data is to be reprogrammed, it is necessary to generate a voltage higher than a read power voltage Vcc by using a booster circuit built in the memory. If the booster circuit is provided with a current supply capacity necessary for erasing data in all memory cells at a time, the power consumption of the booster circuit would greatly increase. This is disadvantageous for products requiring low power consumption.
In order to suppress an increase in power consumption of the booster circuit, there is an idea that a cell array region, from which data is to be erased, is divided into blocks and the data in the blocks is serially and automatically erased for each block.
However, the conventional flash EEPROM with automatic program/erasing functions is not satisfactory in terms of exactness of control of the threshold voltage of the memory cell, performance and reliability.